The present invention relates to wet chemical etching of wafers. In particular, the present invention relates to improved space-saving mask designs that prevent undercutting at feature area corners when forming deep grooves using anisotropic etching methods.
In the semiconductor industry, wafers that have integrated circuits on them are generally separated into chips with a diamond saw, or sometimes by scribing and cleaving. With the recent introduction of chips having micromechanical devices or thin film windows, sawing tends to be wasteful because the devices are fragile and can be easily broken while sawing the wafer. To alleviate this problem, these wafers are separated by scribing and cleaving. Scribe lines are generally made using anisotropic etching techniques, but problems with undercutting arise because the chip corners are not along well-defined crystal planes.
For example, in typical anisotropic etching of silicon (100) wafers, the chip mask patterns are usually bounded by masks with edges along the (111) planes. The (111) planes etch much more slowly than other planes when using certain etchants and thus serve as effective etch-stops along the edges of the chip masks. However, chip corners do not line up with the (111) planes, and although concave corners also serve as etch-stops, convex corners will etch much more quickly than the mask boundaries along the (111) planes. This preferential etching causes considerable undercutting at the convex corners of the chip masks when etching deep grooves.
Corner undercutting is particularly troubling for two types of chip mask patterns. The first pattern has large chip areas, preferably with deep, narrow grooves between the chips. The second pattern has very small chip areas with deep, wide grooves between the chips. The development of corner compensation techniques reduces or eliminates the undercutting of chip corners while etching deep grooves.
The conventional corner compensation method for (100) silicon wafers involves forming a mask extension directed away from a chip mask corner along the (111) direction. The convex corners on the end of the extension are undercut and etched away, causing the extension to shorten. The length of the extension is formed to be completely etched when the groove has reached the proper depth. Etching is stopped before the chip corners are undercut.
Conventional mask extensions are straight and extend from the corners of the mask and lay across the adjacent scribe lines. Since a longer etching time increases the necessary length of the extensions, etching deeper grooves requires the extensions to be longer to avoid undercutting at the corners. Consequently, deeper grooves must also be wider because the extensions must be long and lie across the region where the groove is formed. This wide spacing between the masks due to the length of the extensions results in a large amount of wasted wafer space. This corner compensation technique is also unsuitable for producing high quality scribe lines, which are needed at boundaries between chip areas having delicate micromechanical devices or thin film windows.
Even in small chip patterns, which require deep, wide grooves, and where much unmasked wafer space surrounds the chip masks, the conventional corner compensation technique still may not protect chip corners adequately. Plenty of space exists in these patterns to form long extensions by the conventional technique, but these extensions, unfortunately, are very narrow. Narrow extensions are formed since the extensions are narrower in width than the chip itself, which already has a small area. These long, thin extensions are undercut too rapidly to create deep grooves and preserve the chip corners.
Different variations on the mask extension theme have been developed. The Wu method uses extensions bounded by beveling planes at the chip corners (Wu et al., Sensors and Actuators 18:207 (1989)). Chang et al. describe the use of compensation "streets", in which compensation areas abut the sides of the chips, forming straight extensions at the chip corners at a 45.degree. angle to the chip sides (Solid-State Sensor and Actuator Workshop, June 6-9, 1988). Mayer et al. developed compensation structures in which the main element is a straight masked band extending at an angle from a chip corner (J. Electrochem. Soc. 137:3947 (December 1990)). The two long sides of this band fan out into narrow beams.
All of these corner compensation structures are inadequate for large chip patterns because of space considerations. The mask extensions, whether formed into streets or a fan of beams, or bounded by beveled planes, leave open space that limits the compactness of chips on a wafer. Conventional techniques produce wafers with either deep, narrow grooves and an unacceptable amount of undercutting at convex corners or deep, wide grooves without undercutting at the corners. Both choices have serious deficiencies.
Conventional techniques are also inadequate for small chip patterns, for the mask extensions formed at the convex corners are extremely narrow and undercut too quickly to form deep, wide grooves. In particular, the chip area is too small to permit the formation of an elaborate fan of beams like the Mayer structures. Conventional methods produce either deep, wide grooves with unacceptable undercutting or shallow, wide grooves without undercutting. Again, the choices presented by the conventional compensation techniques do not protect the desired chip patterns.
Thus, a need exists for an improved method of eliminating undercutting at convex corners during the anisotropic etching of wafers. For large or small chip patterns, an improved method would save space on the individual chips and would increase the number of chips that are made from a wafer. Also, the advent of new, mechanically delicate chips requires a gentle method of separating wafers into chips. The present invention solves all these problems by providing a method of making narrow or wide deep grooves without undercutting the chip area corners. A greater variety of elaborate, customized, and microfine structures on wafers become possible using the present invention.